The invention relates to semiconductor processing, in particular to surface cleaning and repair of process-induced damage of low dielectric constant dielectric materials in, for example, damascene processing.
Low dielectric constant (low-k) insulating materials have been integrated into semiconductor devices in order to address reduced feature sizes and high performance requirements. These low-k dielectrics are mechanically weaker than previous generation dielectric materials. The inherently weak nature of the low-k dielectric material can pose significant challenges for downstream electronic-packaging processes and material compatibility.
Low-k materials are, by definition, those semiconductor-grade insulating materials that have a dielectric constant (“k”) lower than that of SiO2, i.e., 3.9. Various types of low-k materials can have dielectric constants ranging from about 3.8-3.6 (e.g., fluorosilicate glass (FSG)), to less than about 3.2 (e.g., (carbon doped oxide (CDO)), to as low as 2.2 (e.g., spin-on glass (SOG)) or even lower, and encompass low-k dielectrics referred to as “ultra low-k” (ULK) and “extreme ultra low-k” (ELK). In many CDO low-k implementations, such as are described herein as one aspect of the invention, suitable carbon-containing low-k materials have a dielectric constant of about 2.7 or lower. To further reduce the size of devices on integrated circuits, it has become necessary to use conductive materials having low resistivity and insulators having low dielectric constants to reduce the capacitive coupling between adjacent metal lines. Low-k materials are being integrated into the devices to improve device performance and allow for device scaling.
Low-k materials are less dense than standard insulating materials such as SiO2. This low density introduces a host of process integration and material compatibility difficulties. Achieving a balance between maintaining a low-k film's integrity, integrating it properly, and performing the necessary stripping, cleaning, and conditioning is challenging. Patterning processes (etching, stripping, deposition, and cleaning) can also have a drastic impact on the integrity of carbon-containing low-k materials, in particular SiOC-based low-k materials.
The properties that give carbon-containing low-k dielectric materials their desirable low dielectric constants are the very same properties that are leading to significant integration challenges. Carbon-containing low-k materials achieve lower dielectric constants through the incorporation of non-polar covalent bonds (e.g., from the addition of carbon) and the introduction of porosity to decrease film density. Introducing porosity or the incorporation of terminal bonds, such as Si—CH3, breaks the continuity of the rigid Si—O—Si lattice of traditional oxides, yielding a lower dielectric constant film that is both mechanically and chemically weaker. Because of the mechanical weakness, carbon-containing low-k films are susceptible to kinetic plasma damage that can undesirably densify the film and thus increase the film's effective k value.
Furthermore, chemical plasmas used in semiconductor processing operations to which dielectrics are exposed can modify carbon-containing low-k films where bonds such as Si—CH3 are readily broken. The susceptibility of carbon-containing low-k materials to plasma modification poses a serious integration challenge since plasma processes are routinely used to etch, clean, and deposit films in the manufacturing of a semiconductor device. In a typical Damascene process flow, prior to metal barrier deposition, process induced carbon-containing low-k dielectric damage can be incurred by a patterned low-k dielectric from (plasma) etch, dry resist strip, wet cleaning and dry cleaning. Carbon-containing low-k materials are also susceptible to the intercalation of plasma species, residues, solvents, moisture, and precursor molecules that can either adsorb into, outgas from, or chemically modify the film. Thereafter, a conductive material, typically a metal, for example copper, is deposited onto the patterned dielectric layer to fill vias and trenches formed in the dielectric layer. Then, excess metal is removed via chemical mechanical polishing (CMP), thereby forming a planar surface comprising regions of exposed copper and low-k dielectric onto which other layers, such as a dielectric barrier, are deposited. The CMP process typically damages the low-k dielectric, resulting in carbon loss and water absorption. This causes the k of the low-k dielectric to increase, thereby lowering the RC improvement that the low-k material can potentially provide.
Also, exposed metal, particularly copper, regions are subject to oxidation prior to the formation of a dielectric barrier or subsequent layers on the wafer surface. And, organic residues of anti-corrosion components of CMP slurry, for example benzotriazole (BTA), may remain on a wafer surface after a CMP process. The presence of copper oxide and organic residue causes problems with the adhesion of the dielectric barrier on the wafer surface. Therefore, various cleaning processes may be used to remove such oxide and residue (another form of process-induced damage). In one specific example, such a wafer may be exposed to a direct plasma in a plasma-enhanced chemical vapor deposition (PECVD) processing chamber for a period of time prior to introducing chemical vapors to the processing chamber. The use of a reducing plasma, such as an ammonia or hydrogen plasma, may reduce copper oxide and hydrocarbons on the surface, thereby cleaning the surface. However, depending upon processing conditions, such direct plasmas also may affect a low-k dielectric surrounding the copper because the low-k material is locally densified at the surface either by ion bombardment or because of bound carbon removal through chemical activity. Some of the k damage induced by operations such as CMP to the low-k material may be recovered by doing a short anneal prior to the above described pre-treatment and etch stop deposition, but the recovery is only marginal.